1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly relates to a semiconductor circuit with a plurality of power supply terminals.
2. Description of the Related Art
A semiconductor IC (integrated circuit) chip is packaged by use of a QFP (Quad Flat Package) package or a SSOP (Shrink Small Outline Package) package in many cases. In case of the QFP package, leads for external input and output are provided on four sides of the package, and in case of the SSOP package, leads are provided on two sides of the package.
The arrangement of power supply terminals and ground terminals in a package with a conventional semiconductor circuit chip 300 will be described with reference to FIG. 1A. Conventionally, a package 1000 with the semiconductor circuit chip 300 is connected to a different semiconductor chip (not shown) on a printed circuit board in order to configure a system. The printed circuit board has a VDD power supply wiring 100 and a VSS power supply wiring 200, which are used to supply power to the semiconductor circuit chip 300. The package 1000 with the semiconductor circuit chip 300 usually includes a first power supply terminal (AVDD) 110 and a first ground terminal (AVSS) 210, which are used to supply a voltage to an analog circuit, and a second power supply terminal (VDD) 120 and a second ground terminal (VSS) 220, which are used to supply a voltage to a digital circuit. Even when the same voltage is supplied to the first power supply terminal (AVDD) 110 and the second power supply terminal (VDD) 120, those terminals are separated as different terminals due to noise countermeasure. Similarly, they are separated as terminals different from the first ground terminal (AVSS) 210 and the second ground terminal (VSS) 220. The first power supply terminal (AVDD) 110 and the second power supply terminal (VDD) 120 are connected at the tip portions of the terminals (leads) to the VDD power supply wiring 100 on the printed circuit board. Similarly, the first ground terminal (AVSS) 210 and the second ground terminal (VSS) 220 are connected at the tip portions of the terminals to the VSS power supply wiring 200 on the printed circuit board. Also, the first power supply terminal (AVDD) 110 is bonded to an electrode pad (AVDD) 11 on the semiconductor circuit chip 300, and the second power supply terminal (VDD) 120 is bonded to an electrode pad (VDD) 12 on the semiconductor circuit chip 300. Similarly, the first ground terminal (AVSS) 210 is bonded to an electrode pad (AVSS) 21 on the semiconductor circuit chip 300, and the second ground terminal (VSS) 220 is bonded to an electrode pad (VSS) 22 on the semiconductor circuit chip 300.
When the package 1000 is assumed to be rectangular, the first power supply terminal (AVDD) 110 and the first ground terminal (AVSS) 210 are arranged on a first side of the package 1000, and the second power supply terminal (VDD) 120 and the second ground terminal (VSS) 220 are arranged on a second side opposing to the first side. Here, the words of the arrangement on the side include a case of the arrangement along the side. Also, the package 1000 has a first corner section and a second corner section which are located on a diagonal line of the rectangle, and the first power supply terminal (AVDD) 110 and the first ground terminal (AVSS) 210 are arranged near the first corner section, and the second power supply terminal (VDD) 120 and the second ground terminal (VSS) 220 are arranged near the second corner section. Moreover, the first power supply terminal (AVDD) 110, the first ground terminal (AVSS) 210, the second power supply terminal (VDD) 120 and the second ground terminal (VSS) 220 are arranged such that a direction from the first power supply terminal (AVDD) 110 to the first ground terminal (AVSS) 210 and a direction from the second power supply terminal (VDD) 120 to the second ground terminal (VSS) 220 are different. At this time, the VDD power supply wiring 100 and the VSS power supply wiring 200 become in the state in which they intersect each other.
FIG. 1B shows a sectional view of a portion at which the VDD power supply wiring 100 and the VSS power supply wiring 200 intersect. Here, at the portion at which the VDD power supply wiring 100 and the VSS power supply wiring 200 intersect, the VSS power supply wiring 200 is connected to a VSS power supply wiring 202 arranged in a different wiring layer through a contact portion 201.
In a printed circuit board on which a package having a semiconductor circuit chip is mounted, a conventional technique is known to prevent the increase in a substrate occupation area of connection wiring due to the arrangement of pins. For example, there is a printed circuit board for trying a noise level drop while suppressing the increase in the substrate occupation area, as described in Japanese Laid Open Patent Publication (JP-P2002-57418A). In this conventional technique, in the printed circuit board, a plurality of pins are electrically connected to electronic parts and are arranged in the shape of a polygon. The pin arranged at the end of the side constituting the shape of the polygon among the plurality of pins is used as a ground terminal. The pin arranged adjacent to this ground terminal is used as a power supply terminal. Moreover, a first conductor region is formed to extend in a radial manner on the same surface as the electronic part from a corner section where the ground terminal in the shape of the polygon is arranged. Thus, the first conductor region and the ground terminal are electrically connected. That is, in this conventional technique, the first conductor region extended in the radial manner from the corner section is used as the wiring.
In the arrangement of the power supply terminal and the ground terminal in the package with the conventional semiconductor circuit chip, a first power supply wiring pattern that the plurality of power supply terminals are connected on the printed circuit board intersects a second power supply wiring pattern that the plurality of ground terminals are connected on the printed circuit board. In order to attain the intersecting of the first power supply wiring pattern and the second power supply wiring pattern, a layer that the first power supply wiring pattern is formed and a layer that the second power supply wiring pattern is formed must be separated at the intersection. Since the layout of the first power supply wiring pattern and the second power supply wiring pattern on the printed circuit board is impossible in the single layer, the layout of a different wiring is made complex, which increases the number of layers and increases the cost of the printed circuit board. In addition, it is necessary to install the contact for the connection between the power supply wiring patterns contained in the different layers. However, the formation of the contact increases the resistance of the wiring, because of the existence of the contact resistance of the portion where the wiring and the contact are connected. Also, at the time of the intersecting between the first power supply wiring pattern and the second power supply wiring pattern, there is a case of making each power supply wiring pattern thinner and protecting the layers of the power supply wirings from being multiplexed. As the power supply wiring pattern is made thinner, the resistance of the thinner portion is increased. Thus, the stable power supply cannot be supplied to the package, and the performance (stability) of the printed circuit board as the system is deteriorated.